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Lead and execute verification of complex SoC subsystems, ensuring robust functionality, performance, power, and security across IP integrations and system interfaces. Own verification strategy, test planning, execution, and sign-off metrics for one or more test-suites features related to subsystem (e.g., Dataflow, RAS, memory/cache, coherency, DMA, interrupts, PCIe/DDR interfaces).
KEY RESPONSIBILITIES
- Define verification strategy and test plans for assigned subsystem(s) including coverage goals, corner cases, and sign-off criteria.
- Develop UVM/SystemVerilog testbenches, sequences, scoreboards, coverage models, checkers, and assertions (SVA).
- Drive constrained-random and directed testing; analyze coverage gaps; create tests to close coverage on functional, code, and assertion metrics.
- Integrate multiple IPs and verify interactions at the subsystem level (coherency, ordering, QoS, virtual channels, power/clock/reset behavior, security/isolation).
- Debug complex issues across RTL, testbench, and interfaces; root-cause failures using waveforms, logs, and assertions.
- Collaborate closely with RTL, architecture, firmware, emulation, and performance teams to refine requirements, align interfaces, and triage bugs.
- Maintain CI/regression infrastructure; optimize simulation performance and triage across large regressions.
- Contribute to methodology improvements, reusable verification components, and best practices across the team.
Requirements
- Strong background in SoC or subsystem verification with hands-on experience in UVM/SystemVerilog–based environments.
- Solid understanding of complex SoC architectures, including memory/cache hierarchies, coherency protocols, interconnects, and high-speed interfaces such as PCIe and DDR.
- Proven ability to define verification strategies, develop reusable testbenches, and drive coverage-driven verification to sign-off.
- Experienced in debugging complex RTL and system-level issues using waveforms, logs, and assertions.
- Comfortable working in cross-functional environments, collaborating with RTL design, architecture, firmware, emulation, and performance teams.
- Self-driven, detail-oriented, and able to take ownership of verification deliverables from planning through execution and sign-off.
- Strong communication skills, with the ability to clearly present verification status, risks, and technical findings to diverse stakeholders.