Staff Silicon Design Engineer

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We are looking for a Staff Design Verification Engineer who will be part of the performance verification team working on next generation of a complex multi-subsystem IP(NBIO Org) for client, server, embedded, graphics, and semi-custom chips. This is a multidisciplinary function/role, working in a close collaboration with IP design and verification managers, system Architects, SOC verification and validation teams on performance aspects of the multi-subsystem IP. We also work closely with performance architects and modelling teams to execute case studies to help HW Architects to drive the design and features definition for the next generation of products.

Key Responsibilities

• Technically lead a small team of engineers, responsible for NBIO performance for various projects
• Collaborate with performance architects, design and verification engineers to understand the new performance features to be verified.
• Create test plan documentation, based on use cases defined by hardware designers and architects, coordinate technical reviews within the team
• Drive regression triage meetings with team, and drive daily scrum for various projects as well as manage backlogs and planning
• Actively involved in developing new ideas to improve the engineering infrastructure, methodology and execution
• Provide technical support to the team to debug both functional and performance test failures to determine the problem's root cause.
• Work with RTL designers and SoC/IP Architects to resolve HW and configuration related performance issues
• Analyze and review performance results with SoC/Chip leads and suggest potential solutions.
• Work on performance case studies with Performance architects, facilitating research through generating results and scripts to analyze results
• Write detailed reports to publish performance results and present them in various management readouts

Preferred Experience

• 5+ years of ASIC design verification experience with strong knowledge of RTL design, verification and Architecture
• Hands on experience with developing or enhancing UVM testbenches and proficient in UVM and SV concepts
• Solid understanding of IP level ASIC design and verification flow from project planning to tape out
• Strong experience in debugging functional or performance issues in the design
• Hands on experience with scrum planning and execution
• Experience with C/C++ and scripting language: Perl, Python, TCL
• Strong problem solving skills
• Bachelors or Master's degree(preferred) in Computer Science/Computer engineering/Electrical Engineering